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decode
- The pipeline SPIN VHDL code (decode part)
execute
- The pipeline SPIN VHDL code (execute part)
fetch
- The pipeline SPIN VHDL code (fetch part)
memory
- The pipeline SPIN VHDL code (memory part)
Pipeline_cpu
- this file contain descr iption of cpu in VHDL language that implies pipeline fetching.
ImprovePipelineAdder
- 基于流水线加法器与寄存器结合在一起的相位累加器设计程序-vhdl implementation of phase accumulator with pipeline and registers.
PipleFullAdder
- 基于流水线的超前进位相位累加器设计程序,速度明显优于无流水线超前进位累加器-vhdl implementation of phase accumulator with pipeline and advanced carry.
CPU
- 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware descr iption language developm
ALU
- a VHDL behavioral descr iption of the two latter two pipeline stages